Speaker: Xi Wang
Date and Location: 3/23, Wen., 11:00AM. CS Conference Room, 206
Title: Concurrent Dynamic Memory Coalescing in GC64 (tentative)
Abstract:

Majority of morden microprocessors are built with multi-level data caches, in order to improve the efficacy of the memory access
through the spatial locality and temporal locality. However, facing the situation that the applications are randomly accessed patterns, the caches will not be as efficient as expected. Targeting this situation, a special architecture is designed without cache,  by using RISC-V ISA as the soft core and Hybrid memory Cube as the main memory in the previous research on the GoblinCore-64(GC-64.)

Whereas, when encoutering the inconsistency of the memory request's address in the GC-64 architecture, especially in the case that processors require the data from multiple hybrid memory cubes, the amount of the memory requests still can not be  effectively coalesced. Thereby, for the purpose of further coalescing the memroy acccess, this research on concurrent dynamic memory coalescing is introduced on the base of the previous memory management unit design. A detailed design of the concurrent dynamic memory coalescing is illustrated , implemented and tested. Results are also been provided to show the efficiency of this concurrent DMC in comparison of the serial MMU in original GC64.