Data-Intensive Scalable Computing Laboratory (DISCL)

Differences

This shows you the differences between two versions of the page.

Link to this comparison view

Both sides previous revision Previous revision
Next revision Both sides next revision
people [2020/04/16 21:25]
xiwang [Ph.D. Students]
people [2020/08/25 10:20]
chenxuniu [Ph.D. Students]
Line 242: Line 242:
     *Concurrent Dynamic Memory Coalescing on GoblinCore-64 Architecture     *Concurrent Dynamic Memory Coalescing on GoblinCore-64 Architecture
  
-|- 
-| style="vertical-align:top;text-align:center;height:30px;" |[[ https://www.linkedin.com/in/brody-williams|Mr. Brody Williams ]] 
  
-|- 
-| style="vertical-align:bottom;text-align:center;height:130px;"| {{ :wiki:photo:sishengliang.png?nolink&100 | }} 
-| style="vertical-align:middle;margin: auto;text-align:left;width: 20%;"| 
-    *Email: Sisheng.Liang@ttu.edu 
-    *Office: EC-302 
- 
-| style="vertical-align:middle;margin: auto;"| 
-    *HPC scheduling 
-    *Machine Learning 
-    *Deep Learning 
- 
-|- 
-| style="vertical-align:top;text-align:center;height:30px;" | Mr. Sisheng Liang 
- 
-Co-directed with Dr. Fang Jin