Data-Intensive Scalable Computing Laboratory (DISCL)

Past Projects

Intelligent I/O Optimizations for High-End Computing

The widely-adopted multicore/manycore architectures have significantly increased the computational performance of high-end computers. However, compared to the processor technology advance, data-access performance improvement has been magnitudes’ slower, which significantly limits the sustained deliverable performance of high-end computing systems. Data access delay, rather than computational speed, has become the major concern of high-end computing. In this research, we investigate intelligent techniques to improve I/O access efficiency for high-end computing. We explore novel data prefetching, data caching, access scheduling, and data layout optimization techniques that considerably reduce the I/O access latency and improve the I/O bandwidth. The objective of this research is three fold: 1) increasing the fundamental understanding of I/O behavior for high-end computing applications; 2) providing novel data-access optimization techniques using scheduling, caching, prefetching, and layout strategies based on the understanding of I/O behavior; 3) improving the productivity of high-end computing applications.

  • H. Song, Y. Yin, Y. Chen and X.-H. Sun. A Cost-Based Application-Specific Data Layout Scheme for Parallel File Systems. In the Proc. of the 20th International Symposium on High Performance Distributed Computing (HPDC'11), 2011. (acceptance rate: 22/170=12.9%). PDF BibTxt Txt
  • Y. Chen, X.-H. Sun, R. Thakur, P. C. Roth and W. Gropp. LACIO: A New Layout-Aware Collective I/O Strategy for Parallel I/O Systems. In the Proc. of IEEE International Parallel and Distributed Processing Symposium (IPDPS'11), 2011. (acceptance rate: 112/571=19.6%). PDF BibTxt Txt
  • Y. Chen, X.-H. Sun, R. Thakur, H. Song and H. Jin. Improving Parallel I/O Performance with Data Layout Awareness. In the Proc. of the IEEE International Conference on Cluster Computing 2010 (Cluster'10), 2010. (acceptance rate: 33/107=30.8%). PDF BibTxt Txt
  • H. Jin, Y. Chen and X.-H. Sun. Optimizing HPC Fault-Tolerant Environment: An Analytical Approach. In the Proc. of the 39th International Conference on Parallel Processing (ICPP'10), 2010. PDF BibTxt Txt
  • X.-H. Sun, Y. Chen and Y. Yin. Data Layout Optimization for Petascale File Systems. In Proc. of The 4th Petascale Data Storage Workshop (PDSW'09), in conjunction with ACM/IEEE SC'09, 2009. PDF BibTxt Txt
  • Y. Chen, S. Byna, X.-H. Sun, R. Thakur, W. Gropp. Hiding I/O Latency with Pre-execution Prefetching for Parallel Applications. In Proc. of the ACM/IEEE Supercomputing Conference (SC'08), Austin, Texas, USA, Nov. 2008. (Best Paper finalist, Best Student Paper finalist). (acceptance rate: 59/277=21.3%). PDF BibTxt Txt
  • S. Byna, Y. Chen, X.-H. Sun, R. Thakur, W. Gropp. Parallel I/O Prefetching Using MPI File Caching and I/O Signatures. In Proc. of the ACM/IEEE Supercomputing Conference (SC'08), Austin, Texas, USA, Nov. 2008. (acceptance rate: 59/277=21.3%). PDF BibTxt Txt
  • Y. Chen, S. Byna, X.-H. Sun, R. Thakur, W. Gropp. Exploring Parallel I/O Concurrency with Speculative Prefetching. In Proc. of the 37th International Conference on Parallel Processing (ICPP'08), Portland, Oregon, USA, 2008. (acceptance rate: 81/263=30.8%). PDF BibTxt Txt
  • S. Byna, Y. Chen and X.-H. Sun. A Taxonomy of Data Prefetching Mechanisms. In Proc. of International Symposium on Parallel Architectures, Algorithms, and Networks (ISPAN'08), 2008. PDF BibTxt Txt
  • X.-H. Sun, S. Byna and Y. Chen. Server-based Data Push Architecture for Multi-processor Environments. Journal of Computer Science and Technology (JCST), Vol. 22, No. 5, 641 – 652, 2007. PDF BibTxt Txt
  • X.-H. Sun, S. Byna, and Y. Chen. Improving Data Access Performance with Server Push Architecture. In Proc. of the NSF Next Generation Software Program Workshop (in conjunction with IPDPS'07), March 2007. PDF BibTxt Txt

Performance Modeling and Evaluation of Parallel Systems and Applications

Scalability is a key factor of the design of parallel systems and algorithms. However, conventional scalabilities are designed for homogeneous parallel processing. In this project, we propose a generalized scalablity model, named isospeed-efficiency model, to characterize and evaluate general (both homogeneous and heterogeneous computing systems) parallel systems and algorithms. Through theoretical analysis, we derive methodologies of scalability measurement and prediction for general parallel systems. Experimental results verify the analytical results and confirm that the generalized scalability works well in both homogeneous and heterogeneous environments. Based on the theoretical modeling and analyses, we design a Scalability Testing and Analysis System (STAS) and provide a prototype implementation. STAS provides the facility to conduct automated scalability measure and analysis. It reduces the burden for users to evaluate the performance of algorithms and systems.

  • Y. Chen, X.-H. Sun and M. Wu. Algorithm-System Scalability of Heterogeneous Computing. Journal of Parallel and Distributed Computing (JPDC), Vol. 68, No. 11, 1403 – 1412, 2008. JPDC online version PDF BibTex Txt
  • Y. Chen and X.-H. Sun. STAS: A Scalability Testing and Analysis System. In Proc. of IEEE International Conference on Cluster Computing 2006(Cluster'06), Sept. 2006. (acceptance rate: 42/127=33.1%). PDF BibTex Txt
  • X.-H. Sun, Y. Chen and M. Wu. Scalability of Heterogeneous Computing. In Proc. of 34th International Conference on Parallel Processing (ICPP'05), June 2005. (acceptance rate: 69/241=28.6%). PDF BibTex Txt

Design Information Framework Project

Design Information Framework (DIF) is a platform that facilitates cross-disciplinary sharing of research and development information. This project was led by Prof. Keiichi Sato of IIT Institute of Design, and please see Prof. Sato's website for more details. We implemented the DIF system primarily with JDK 1.4.2 and open-source database system MySQL 4.2 with 45K+ lines of code.

  • E.-C. Jung, K. Sato, Y. Chen, X. He, T. MacTavish and D. Cracchiolo. DIF Knowledge Management System: Bridging Viewpoints for Interactive System Design. In Proc. of 11th International Conference on Human-Computer Interaction (HCI'05). Las Vegas, July 2005. PDF BibTex Txt

Research and Development of Integrated User Environment Tools for Supercomputers

This project was led by Prof. Guoliang Chen and Prof. Hong An at National High-Performance Computing Center (at HeFei) in University of Science and Technology of China. We designed and implemented a remote parallel debugger for large-scale supercomputers. The debugger leverages the functionality of two serial debuggers, gdb and dbx, and integrates parallel debugging features. The debugger was developed with C, Java & CORBA (for user interface and the communication between remote users and supercomputers). In addition, we studied and compared two dominant parallel programming models, Single Memory Model (such as MPI) and Hybrid Memory Model (such as MPI+OpenMP), proposed effective way of utilizing these two models, and verified the proposed strategies with experimental testing on Dawning3000 supercomputer, one of the leading supercomputers in China at that time.

  • Y. Chen, G. Chen, C. Li and J. He. Hybrid Programming Model Research on SMP Cluster Architecture. Mini-Micro Systems, Vol.25, No.10 P.1763-1767. 2004. (In Chinese)
  • Y. Chen, C. Li, H. An, Q. Zheng and Z. Chen. Remote Parallel Debugger Based on Dawning3000 Parallel Machine. Journal of Computer Science, Vol.31, No.3, P.179-182. 2004. (In Chinese)
  • Y. Chen, K. He, Z. Lu and C. Yan. Design and Implementation of A Parallel Debugger for Cluster System. Journal of Computer Engineering, Vol.30, No.9, P.50-52. 2004. (In Chinese)
  • Y. Chen, G. Chen, Y. Xu and J. Shan. Implementation and Evaluation of MPI+OpenMP Programming Model on Dawning3000. In Proc. of the 21st IASTED International Conference, Applied Informatics. Innsbruck, Austria. 732-737. 2003. PDF BibTex Txt